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  • RISC-V Microarchitectural Design-Space Exploration in Chipyard

    calendar Dec 15, 2024 · 3 min read · RISC-V Chipyard BOOM Rocket Chip Memory Hierarchy Branch Prediction Performance Analysis  ·
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    ECE 5504 — Computer Architecture · Virginia Tech · Fall 2024 Team project with Alok Mehendale and Benjamin Rice. Benchmarks were divided between us: Alok took rsort and vvadd, Benjamin took towers and median, and I took FFT and SHA-256. Results were combined for the final report. Problem General-purpose processor …


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Pranav Kumar

Open Source Contributer, Engineer, Perpetual student, reader, builder.
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Featured Posts

  • Road Rage: An FPGA Real-Time Game in SystemVerilog
  • FUSE: Single-Pass Binary Co-Instrumentation for Accurate Vulnerability Detection
  • Floating-Point Arithmetic: Performance vs. Area on an FPGA
  • Concurrent Data Structures: Memory Reclamation Benchmarking (SEIZE)
  • STSPIN220 Stepper Driver Library for Arduino

Recent Posts

  • Daily Dial — a 24-Hour Time-Tracking Chrome Extension
  • JobHakken — a Local-First Job Search Application
  • File System Consistency Checker (xv6 fsck)
  • IoT Security Case Study: Edge AI & Federated Learning in Smart Grids
  • Virtual Memory Analysis: Page Table Walker
  • Advanced Linux Kernel Modules & Performance Monitoring
  • LLVM Optimization Passes: Function Analysis & Local Optimizations
  • Register Allocation Optimization through Coalescing & Live Range Splitting

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