<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>DE1-SoC on Pranav Kumar</title><link>https://pranav083.github.io/tags/de1-soc/</link><description>Recent content in DE1-SoC on Pranav Kumar</description><generator>Hugo -- gohugo.io</generator><language>en</language><copyright>Copyright © 2016–2030, Pranav Kumar</copyright><lastBuildDate>Tue, 05 May 2026 00:00:00 -0400</lastBuildDate><atom:link href="https://pranav083.github.io/tags/de1-soc/index.xml" rel="self" type="application/rss+xml"/><item><title>Road Rage: An FPGA Real-Time Game in SystemVerilog</title><link>https://pranav083.github.io/post/project/road-rage-rtl/</link><pubDate>Tue, 05 May 2026 00:00:00 -0400</pubDate><guid>https://pranav083.github.io/post/project/road-rage-rtl/</guid><description>
&lt;p&gt;&lt;strong&gt;ECE 4515 — Digital Design II · Virginia Tech · Spring 2026&lt;/strong&gt;
&lt;strong&gt;Team project&lt;/strong&gt; with Rahul Muthuraman Shanmugam.&lt;/p&gt;
&lt;p&gt;A top-down lane-dodge racing game, implemented entirely in hardware on a Terasic DE1-SoC (Cyclone V 5CSEMA5F31C6). No processor, no software — the game is a state machine driving datapath modules at pixel rate.&lt;/p&gt;
&lt;hr&gt;
&lt;h2 id="why-build-a-game-in-rtl"&gt;Why build a game in RTL&lt;/h2&gt;
&lt;p&gt;A game is a deceptively good digital design exercise. It forces real-time constraints that cannot be missed (a VGA scanline waits for nobody), multiple interacting state machines, memory-backed graphics, asynchronous inputs that must be synchronised and debounced, and a pipeline whose latency has to be accounted for exactly — because a one-cycle error shows up as a visible column of wrong pixels.&lt;/p&gt;</description></item></channel></rss>