Master's Projects Portfolio
Dec 18, 2025 · 4 min read · Systems Compilers Operating Systems Security Concurrent Programming Hardware Architecture ·Welcome to my graduate research and coursework portfolio. This page showcases projects across 3 semesters of my master's degree, spanning computer architecture, systems programming, compiler optimization, operating systems, and distributed systems security. Semester 1 (Fall 2024) - Computer Architecture & Hardware …
Read MoreConcurrent Data Structures: Memory Reclamation Benchmarking (SEIZE)
Nov 15, 2025 · 10 min read · Concurrent Programming Lock-Free Algorithms Memory Management Rust Benchmarking Performance Analysis Data Structures ·Concurrent Data Structures: Memory Reclamation Benchmarking (SEIZE) Course: Advanced Systems - Concurrent Programming | Semester: Fall 2025 Technical Focus: Lock-Free Algorithms, Memory Safety, Performance Analysis Problem Statement & Motivation Lock-free data structures eliminate mutex bottlenecks but create memory …
Read MoreFile System Consistency Checker (xv6 fsck)
Nov 15, 2025 · 10 min read · Operating Systems File Systems Data Integrity Crash Consistency RISC-V Kernel Programming File System Recovery ·Course: CS 5204 - Advanced Operating Systems Project 1 | Semester: Fall 2025 Technical Focus: Crash Consistency, File System Reliability, Recovery Algorithms Problem Statement & Motivation File systems can become corrupted when systems crash mid-operation. xv6's simple inode/block-based design is vulnerable to …
Read MoreIoT Security Case Study: Edge AI & Federated Learning in Smart Grids
Nov 15, 2025 · 12 min read · Security Privacy IoT Machine Learning Energy Systems Regulatory Compliance Threat Analysis ·Course: IoT Security & Privacy | Semester: Fall 2025 Technical Focus: Threat Modeling, Privacy-Preserving ML, Critical Infrastructure Protection Problem Statement & Motivation The electrical grid is critical national infrastructure (150M+ customers). Modernization through smart grid technology introduces connectivity …
Read MoreVirtual Memory Analysis: Page Table Walker
Nov 15, 2025 · 8 min read · Operating Systems Virtual Memory Page Tables Kernel Programming Memory Analysis Linux Internals MMU Management ·Course: CS 5204 - Advanced Operating Systems Project 2 | Semester: Fall 2025 Technical Focus: Virtual Memory Management, Page Table Structures, TLB Behavior Problem Statement & Motivation Modern systems use multi-level page tables for virtual-to-physical (VA→PA) address translation. Understanding memory layout is …
Read MoreAdvanced Linux Kernel Modules & Performance Monitoring
May 15, 2025 · 8 min read · Systems Kernel Development Rust Memory Management Performance Monitoring Device Drivers Fuzzing Security Testing ·Course: Advanced Linux Kernel | Semester: Spring 2025 Technical Focus: Kernel-Space Systems, Memory Allocation Strategies, Device Driver Architecture Problem Statement & Motivation Kernel development traditionally requires unsafe C for performance; safety violations cause system crashes. Rust in Linux kernel (since …
Read MoreLLVM Optimization Passes: Function Analysis & Local Optimizations
May 15, 2025 · 10 min read · Compilers LLVM Compiler Optimization IR Analysis Code Generation Loop Analysis Optimization Passes ·Course: Compiler Optimization | Semester: Spring 2025 Technical Focus: IR Analysis, Pass Infrastructure, Optimization Algorithms Problem Statement & Motivation LLVM's optimization infrastructure provides extensibility but lacks accessible tutorials for custom passes. Students must navigate complex APIs: Function, …
Read MoreRegister Allocation Optimization through Coalescing & Live Range Splitting
May 15, 2025 · 11 min read · Compilers Register Allocation Code Generation LLVM Optimization Compiler Algorithms Performance Tuning ·Course: Compiler Design - Advanced Topics | Semester: Spring 2025 Technical Focus: Graph Coloring, Register Pressure, Code Generation Problem Statement & Motivation Register allocation is the compiler's final opportunity to improve code quality before machine code generation. Modern CPUs have 16-32 integer registers, …
Read MoreCache Optimization on RISC-V Architecture
Dec 15, 2024 · 10 min read · Hardware Architecture Cache Design RISC-V Performance Benchmarking Memory Subsystem Hardware Simulation Replacement Policies ·Course: ECE 5504 - Computer Architecture | Semester: Fall 2024 Technical Focus: Memory Hierarchy Design, Replacement Algorithms, Performance Modeling Problem Statement & Motivation Cache design involves fundamental trade-offs between performance and hardware complexity. Least Recently Used (LRU) replacement achieves …
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