Road Rage: An FPGA Real-Time Game in SystemVerilog
May 5, 2026 · 3 min read · FPGA SystemVerilog RTL Design DE1-SoC Cyclone V VGA Quartus Hardware Design ·ECE 4515 — Digital Design II · Virginia Tech · Spring 2026 Team project with Rahul Muthuraman Shanmugam. A top-down lane-dodge racing game, implemented entirely in hardware on a Terasic DE1-SoC (Cyclone V 5CSEMA5F31C6). No processor, no software — the game is a state machine driving datapath modules at pixel rate. Why …
Read MoreFloating-Point Arithmetic: Performance vs. Area on an FPGA
Apr 20, 2026 · 3 min read · FPGA SystemVerilog Floating Point Pipelining Design Space Exploration Cyclone V Quartus Hardware Design ·ECE 4515 — Digital Design II · Virginia Tech · Spring 2026 A hardware design-space exploration: build the same floating-point datapath at different pipeline depths, synthesise each on a Cyclone V, and measure what the extra performance actually costs in silicon. The question Deeper pipelines let a datapath run at a …
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